RapidRTL: Online VHDL & Verilog to Schematic and Simulator

RapidRTL is a free, browser-based tool that instantly converts VHDL, Verilog, and SystemVerilog code into interactive circuit schematics, and simulates them clock by clock with no testbench. No installation, no signup: paste your HDL code and see the schematic in seconds.

How It Works

Write or paste HDL code: Supports VHDL (87/93/00/02/08), Verilog, and SystemVerilog with smart snippet inference.
Click Generate: Your code is synthesised using industry-standard Yosys and GHDL tools.
Explore the schematic: Pan, zoom, and inspect individual cells in the interactive diagram.
Simulate: Run the circuit clock by clock with no testbench. Click an input in the waveform to change it, and every wire on the schematic shows its value.

Key Features

Smart Snippet Inference: No need to write full module/entity boilerplate. RapidRTL automatically infers ports and wraps your code.
Online Simulation: A waveform for every input, output and register, up to 64 cycles, with state machines shown by state name. No testbench to write.
FPGA Vendor Targets: Synthesise for Xilinx 7-Series, Lattice iCE40/ECP5, Gowin, or Intel Cyclone IV and V.
Gate-Level Decomposition: Drill down from high-level cells (MUX, adders, flip-flops) to AND/NOT primitives.
Critical Path Analysis: Visualise the longest combinational path and identify timing bottlenecks.
Latch Detection: Automatic warnings when unintended latches are inferred from your code.
Resource Statistics: See gate counts, flip-flop usage, and LUT utilisation at a glance.
Dark & Light Themes: Comfortable viewing in any environment.
Mobile Responsive: Works on tablets and phones with a dedicated mobile inspector.

Who Is RapidRTL For?

Students learning digital logic design and HDL languages
Engineers prototyping circuits without heavy vendor tools
Educators demonstrating combinational and sequential logic in lectures
Hobbyists exploring FPGA development and hardware description

Supported Languages

RapidRTL supports the three major hardware description languages used in digital design:

VHDL: Standards 87, 93, 00, 02, and 08. Includes automatic Synopsys library detection.
Verilog: IEEE 1364 compliant with full synthesis support.
SystemVerilog: Synthesisable subset for modern digital design.

Powered by Open-Source Tools

RapidRTL uses industry-proven open-source synthesis tools under the hood:

Yosys: The open synthesis suite for Verilog and SystemVerilog.
GHDL: The open-source VHDL analyser and compiler.
netlistsvg: Converts JSON netlists into clean SVG schematics.

Get started now: type or paste your HDL code above and click Generate.