Learn digital design with live circuits

Guides to Verilog, SystemVerilog and VHDL where the circuits aren't pictures; they're synthesized from the code on the page. Zoom into them, and where you see a Run button, change the code and watch the hardware change.

• Moore vs Mealy FSM in Verilog, and how to encode states
  The three-part FSM idiom on a live schematic, a sequence detector as Moore and as Mealy with waveforms, and when one-hot encoding earns its registers.
  VerilogSystemVerilog
• Signal vs variable in VHDL: the difference (<= vs :=)
  The difference between a signal and a variable in a VHDL process, shown on a schematic and a waveform, and the rules for choosing between them.
  VHDL
• What causes inferred latches in Verilog (and how to fix them)
  Why a missing else or case default makes synthesis infer a latch, what it looks like in the netlist and in simulation, and the three ways to fix it.
  VerilogSystemVerilog
• Simulate Verilog and VHDL without a testbench
  Run a Verilog or VHDL design clock by clock with no testbench: the clock and reset are driven for you, and you set inputs by clicking the waveform.
  VerilogVHDL
• How to view Verilog and VHDL as a schematic: the tools compared
  Every common way to see HDL as a circuit diagram: Vivado and Quartus netlist viewers, Yosys show and netlistsvg, DigitalJS, EDA Playground, TerosHDL, Sigasi and RapidRTL, compared by language, install and what each one draws.
  VerilogSystemVerilogVHDL
• What synthesis does to Verilog: the netlist after every pass
  A 4-bit counter followed through synthesis: the parsed process, multiplexers and a flip-flop, gates and Xilinx primitives, compared with Vivado's netlists.
  Verilog
• FIR filter in VHDL: a moving average, from equation to FPGA
  A moving average FIR filter in VHDL, from equation to hardware: a register, an adder, a divide by two that costs no logic, and Vivado's LUTs and carry chains.
  VHDL
• VHDL data types: std_logic_vector, unsigned, signed, integer
  The synthesizable VHDL data types, their ranges and when to use each: std_logic, std_logic_vector, unsigned, signed, integer, boolean and enumerations.
  VHDL
• VHDL type conversion: std_logic_vector, integer, unsigned
  How to convert between std_logic_vector, integer, unsigned and signed in VHDL: a conversion table, to_integer, to_unsigned, to_signed and resize.
  VHDL
• Ripple-carry vs carry-lookahead adders in Verilog
  The ripple-carry adder at gate level on a live schematic, why its carry chain sets the clock speed, carry-lookahead and carry-select, and when to write +.
  Verilog
• The always_comb latch error, explained and fixed
  Why SystemVerilog's always_comb refuses to build a latch, what 'Latch inferred for signal' means, why always @(*) latches silently instead, and the fixes.
  SystemVerilog
• Blocking vs nonblocking assignment in Verilog (= vs <=)
  What = and <= do: a one-character edit turns a shift register into a different circuit, and two rules keep simulation matching hardware.
  VerilogSystemVerilog
• Button debouncing in Verilog: synchronizer and counter
  Why a raw button breaks your logic twice (bounce and metastability), and the standard fix on a live schematic: a two-flop synchronizer and a counter.
  Verilog
• case, casez and casex in Verilog, SystemVerilog and VHDL
  What case, casez and casex do, why style guides ban casex, SystemVerilog's unique, priority and case inside, and VHDL's case and case? compared.
  VerilogSystemVerilogVHDL
• Clock domain crossing: why the synchronizer is two flip-flops
  What happens when a signal crosses clock domains, why one flip-flop isn't enough, the two-flop synchronizer on a live schematic, and the multi-bit trap.
  VerilogSystemVerilogVHDL
• Multiplier architectures in Verilog: why * is expensive
  A 4-bit multiplier at gate level on a live schematic, the partial-product array, the shift-add alternative, and what Booth recoding and DSP blocks change.
  Verilog
• Priority arbiter in Verilog: if-else, casez and a one-liner
  A fixed-priority arbiter three ways (the if-else chain, casez, and the two's-complement one-liner) on live schematics, plus round-robin and the pitfalls.
  Verilog
• VHDL procedure vs function, and what each synthesizes to
  What separates a VHDL function from a procedure, what each becomes in hardware, live schematics of both, and the parameter-class rules that trip people up.
  VHDL
• What causes inferred latches in VHDL (and how to fix them)
  Why an if without else in a VHDL process infers a latch, what it looks like in the netlist (on a live schematic), and the idioms that prevent it.
  VHDL