Learn digital design with live circuits

Guides to Verilog, SystemVerilog and VHDL where the circuits aren't pictures; they're synthesized from the code on the page. Zoom into them, and where you see a Run button, change the code and watch the hardware change.

• Adder architectures: what + actually builds
  The ripple-carry adder at gate level on a live schematic, why the carry chain sets your clock speed, carry-lookahead and carry-select explained, and when to just write +.
  Verilog
• The always_comb latch error, explained and fixed
  Why SystemVerilog's always_comb refuses to build a latch, what 'Latch inferred for signal' means, how the same code silently latches under always @(*), and the fixes.
  SystemVerilog
• Blocking vs nonblocking assignment in Verilog (= vs <=)
  What = and <= actually do, shown by turning a shift register into a different circuit with a one-character edit, and the two rules that keep simulation matching hardware.
  VerilogSystemVerilog
• Debouncing a button in Verilog, properly
  Why a raw button breaks your logic twice (bounce and metastability), and the standard fix on a live schematic: a two-flop synchronizer feeding a stability counter.
  Verilog
• case vs casez vs casex (and the VHDL and SystemVerilog versions)
  What Verilog's three case statements actually do, why casex is banned in most style guides, SystemVerilog's unique, priority and case inside, and VHDL's case and case? compared.
  VerilogSystemVerilogVHDL
• Clock domain crossing: why the synchronizer is two flip-flops
  What actually happens when a signal crosses clock domains, why one flip-flop isn't enough, the standard two-flop synchronizer on a live schematic, and the multi-bit trap.
  VerilogSystemVerilogVHDL
• FSM design in Verilog: Moore vs Mealy, and how to encode states
  The three-part state machine idiom on a live schematic, a sequence detector with overlap, Moore vs Mealy compared honestly, and when one-hot encoding earns its registers.
  VerilogSystemVerilog
• Multiplier architectures: why * is expensive
  A 4-bit multiplier at gate level on a live schematic, the partial-product array explained, the sequential shift-add alternative, and what Booth recoding and DSP blocks change.
  Verilog
• Priority arbiters in Verilog, from if-else to the one-liner
  Design a fixed-priority arbiter three ways (the if-else chain, casez, and the two's-complement one-liner) with live schematics, plus the round-robin extension and the classic pitfalls.
  Verilog
• Procedures vs functions in VHDL (and what they synthesize to)
  What separates a VHDL function from a procedure, what each becomes in hardware, live schematics of both, and the parameter-class rules that trip people up.
  VHDL
• Variables vs signals in VHDL processes (:= vs <=)
  Why signal assignments wait and variable assignments don't, shown by a shift register that loses a flip-flop, and the rules for choosing between them.
  VHDL
• What causes inferred latches in VHDL (and how to fix them)
  Why an if without else in a VHDL process makes synthesis infer a latch, what it looks like in the netlist (on a live schematic), and the idioms that prevent it.
  VHDL
• What causes inferred latches in Verilog (and how to fix them)
  Why a missing else or case default makes synthesis infer a latch, what it looks like in the netlist (shown on a live schematic), and the three ways to fix it.
  VerilogSystemVerilog