Multiplier architectures: why * is expensive

Updated 2026-08-15 · The schematics below are live: zoom and pan them, and where there's a Run button, edit the code and watch the circuit change.

If the adder guide showed that + isn’t free, this one turns the dial up. Multiplication is the most expensive operator you’ll routinely write, and unlike addition, the cost is hard to miss once you see it drawn.

What * builds

One *, two 4-bit inputs, rendered at gate level. Zoom out first, then zoom back in:

Interactive schematic by RapidRTL

For scale: the same 4 bits through the adder guide’s + produced roughly half this logic. And the gap grows quadratically, because a multiplier is built out of adders.

The structure: school arithmetic, in binary

Write out 13 × 11 on paper and you produce one shifted row per digit, then add the rows. Binary multiplication is the same algorithm with an easier inner step, because multiplying by a bit is just AND:

        1101      a
      × 1011      b
      ------
        1101      a AND b[0]
       1101       a AND b[1], shifted left 1
      0000        a AND b[2], shifted left 2
     1101         a AND b[3], shifted left 3
    --------
    10001111      sum of the four rows

That’s the whole combinational multiplier: an AND array producing N rows of partial products (N² AND gates), and a reduction summing the rows (roughly N adders). Both halves are visible in the schematic above. For an N×N multiply you’re paying quadratic area, and the reduction is a stack of carry chains, so the delay is substantial too.

The other end of the trade: shift-add

If the array multiplier spends area to finish in one (long) cycle, the classic alternative spends time instead: one adder, used N times. Each cycle examines one multiplier bit, conditionally adds the shifted multiplicand into an accumulator, and shifts:

Interactive schematic by RapidRTL

Compare the two schematics: the array’s field of gates has collapsed into one adder, two shift registers, and a small controller (a cousin of the machines in the FSM guide). The price is N cycles per multiply and a done handshake instead of an always-valid output. Area versus latency, the same axis as the adder architectures, just with a bigger lever.

Making the array cheaper: two names to know

• Booth recoding attacks the rows. By examining multiplier bits in overlapping pairs and allowing subtractions as well as additions, it roughly halves the number of partial products, and handles signed numbers naturally. It’s why “how do you multiply signed values?” has a better answer than sign-extending everything.
• Wallace and Dadda trees attack the summing. Instead of adding rows one after another (a chain of carry chains), layers of small adders compress all rows in parallel, in logarithmic depth, with one fast adder at the end. This is the multiplier equivalent of the adder guide’s ripple-to-prefix upgrade.

You will rarely hand-build either; synthesis tools apply both when you write * with timing constraints. The names matter because they’re what the tool’s choices, and interview follow-ups, are called.

The FPGA honesty section

Modern FPGAs embed hard DSP blocks: silicon multipliers (typically around 18×18) with built-in accumulators, placed around the fabric precisely because LUT-built multipliers are so costly. Writing * lets the tools map onto them; the schematic above is what your design pays only when the DSPs run out, or when your product terms don’t fit their width. The practical checklist:

• Write * and let the mapper use DSP blocks; check the utilization report to see whether it did.
• Widths drive everything. A 20×20 multiply needs multiple 18×18 blocks stitched together; trimming operands to what the data actually needs saves whole DSPs, not just gates.
• Constants are special. Multiplying by a constant becomes shifts and adds (x * 10 is (x << 3) + (x << 1)), often free of DSPs entirely; tools do this for you, and it’s why constant coefficients are cheap in filters.
• Need one multiply per sample, not per clock? The shift-add shape, or time-multiplexing one DSP across channels, trades your spare cycles for area exactly as above.