RapidRTL
Adder architectures: what + builds
a + b looks free. It’s one character, and every HDL accepts it. But
somewhere below that character is a circuit whose shape somebody had to
choose, and the choice decides how fast your whole design can clock.
Adders are the first place where architecture, the same logic built in
different shapes, really matters, which also makes them a favourite
interview topic.
What + builds
Here is a single +, rendered at gate-level detail, and kept deliberately
small: two bits plus a carry-in, so the structure is actually readable.
Each bit computes a sum and passes a carry up to the next; that diagonal
path is the whole story of this page. When you’ve followed it, do what the
comment says: widen both part-selects to [3:0] and press Run. Same
one character, twice the chain:
Interactive schematic by RapidRTL
Ripple-carry, spelled out
The structure hiding in that schematic is a full adder per bit: sum is a three-way XOR, and carry-out is “two or more of the three inputs are 1”. Written explicitly:
Interactive schematic by RapidRTL
Ripple-carry is the smallest adder you can build, and its cost is time: bit 3’s sum isn’t valid until the carry has passed through bits 0, 1 and 2. The delay grows linearly with width. At 4 bits nobody cares; at 64 bits, that chain of carry logic is likely the longest path in your design, and the longest path is what sets your maximum clock frequency. (Open either schematic in the editor and run the critical-path view: the timing tool traces exactly this chain.)
Carry-lookahead: buying speed with logic
The fix starts with a change of vocabulary. For each bit, compute two signals that don’t depend on the carry at all:
- Generate:
g = a & b(this bit creates a carry regardless) - Propagate:
p = a ^ b(this bit passes along an incoming carry)
Then every carry can be written directly. Carry into bit 2, say, is “bit 1 generated, or bit 1 propagated something bit 0 generated, or both propagated the carry-in”:
assign c1 = g0 | (p0 & cin);
assign c2 = g1 | (p1 & g0) | (p1 & p0 & cin);Nothing waits for a ripple; each carry is computed from the inputs in a couple of gate delays. The price is that the expressions grow with bit position, so wide lookahead adders are built hierarchically, in blocks of 4, and the fully parallel versions of this idea (prefix adders such as Kogge-Stone) reach every carry in logarithmic depth at the cost of serious area and wiring. Linear time for minimal area, or logarithmic time for a lot more: that’s the trade, and every adder architecture is a point on it.
Carry-select: the pragmatic middle
One more classic worth knowing by name. Split the adder in half; the top half can’t start until it knows its carry-in, so compute both answers, one assuming carry-in 0 and one assuming 1, and let the real carry pick via a mux. You pay one extra half-adder and a mux to cut the worst-case path roughly in half, and the idea stacks into multiple blocks.
When to just write +
Honesty section. On FPGAs, the fabric has dedicated carry chains:
hardened, fast paths between adjacent cells built precisely for ripple
carries. A plain + maps onto them and will beat any clever adder you
hand-build out of general-purpose LUTs, so on FPGA the right architecture
is almost always the one character. Synthesis tools for ASICs likewise
pick adder architectures from timing constraints.
So why learn this? Because the timing report doesn’t explain itself. When the critical path of your design runs through an adder, these are the options the tool weighed, “make the adder wider” has a real cost you can now name, and pipelining across an adder makes sense once you see it as a chain of stages rather than one character. The architectures also come straight back the moment you build anything from adders, which is the subject of the multiplier guide.