Viewing Verilog and VHDL as a schematic

Updated 2026-10-16

A schematic of HDL code is drawn from a netlist: a tool elaborates or synthesizes the code into cells and the wires between them, then lays the graph out as a diagram. Tools differ in which netlist they draw (generic RTL cells, logic gates, or the primitives of one FPGA family), which languages they read, and what they need installed.

This page lists the common options and compares them. For what the netlist looks like at each stage of synthesis, see what synthesis does to Verilog.

The options

RapidRTL is the tool this site belongs to.

Vivado and Quartus

The vendor tools draw the netlist for one device, so they show exactly which primitives a design uses on that part. Both need a project with a device selected.

• Vivado. Flow Navigator → RTL Analysis → Open Elaborated Design → Schematic draws generic cells such as RTL_ADD and RTL_REG. After synthesis, Open Synthesized Design → Schematic draws the Xilinx primitives: LUT, FDRE, CARRY4, and a buffer on every pin.
• Quartus Prime. Tools → Netlist Viewers holds the RTL Viewer, available after Analysis & Elaboration, the Technology Map Viewer, after mapping or after fitting, and the State Machine Viewer.

Both installs are large, and the schematic is one view among many in a full FPGA flow.

Yosys from the command line

Yosys is an open-source synthesis tool. Its show command draws the netlist after any pass with Graphviz, which must be installed:

yosys -p "read_verilog counter.v; proc; opt; show -format svg -prefix counter"

netlistsvg draws a Yosys netlist with gate and flip-flop symbols instead of Graphviz boxes. Yosys writes the netlist as JSON first:

yosys -p "read_verilog counter.v; prep -top counter; write_json counter.json"
netlistsvg counter.json -o counter.svg

For VHDL, the GHDL plugin reads the code into Yosys:

yosys -m ghdl -p "ghdl counter.vhd -e counter; prep -top counter; write_json counter.json"

This route can be scripted, for documentation or for a check in CI. Each tool is installed separately.

In the browser

• DigitalJS synthesizes Verilog and SystemVerilog with Yosys, in the browser or on its server, and simulates the circuit: inputs can be set and outputs watched as the clock runs. It does not read VHDL.
• EDA Playground is an online simulator. Its Yosys synthesis flow can draw a circuit diagram of a design with one top module. Running code needs a free account.
• RapidRTL draws the netlist that Yosys and GHDL produce from Verilog, SystemVerilog or VHDL. A snippet can be pasted without the module or entity around it, and the ports are inferred. The same code can be drawn as written, optimised, as gates, or mapped to Xilinx 7-series, Lattice iCE40 or ECP5, Gowin or Intel FPGAs. It does not simulate.

In VS Code

• TerosHDL is a general HDL toolbox: linting, documentation, a hierarchy viewer, a Verilog and SystemVerilog schematic viewer, and a state machine viewer.
• DigitalJS has VS Code extensions that synthesize and simulate a circuit inside the editor, for Verilog and SystemVerilog.
• Sigasi Visual HDL draws block diagrams and state machines from the code as it is typed, including unfinished code. A block diagram shows instances and processes, not the gates they synthesize to.
• RapidRTL draws the schematic inside VS Code with tools bundled in the extension, so the code never leaves the machine. Pro adds tracing between code and schematic in both directions, FPGA family mapping, and a redraw on every save.

Choosing one